Clik here to view.
Check out the Intel® Advisor XE 2013 Update 3..
Intel® Advisor XE 2013 Update 3 guides developers to add parallelism to their existing C/C++ programs. Using this tool, you can identify where most of the time is spent in your code, which of those...
View ArticleClik here to view.
Register for Intel® Software Tools Spring Technical Webinar Presentation...
I will be presenting on May 14th at 11am PDT on the following topic:Design and prototype scalable threading using Intel® Advisor XEPlease register for this presentation using the following...
View ArticleClik here to view.
Modern locking
Modern lockingMost multi-threaded software uses locking. Lock optimization traditionally has aimed to reduce lock contention, that is make the critical regions smaller. In optimized software, this...
View ArticleClik here to view.
Intel(r) Transactional Synchronization Extensions (Intel(r) TSX) profiling...
Intel TSX exposes a speculative execution mode to the programmer to improve locking performance.. Tuning speculation requires heavily on a PMU profiler. This document describes TSX profiling using the...
View ArticleClik here to view.
Speeding Up Your Cloud Environment On Intel® Architecture
In my previous blog, I discussed “Ways to Speeding up Your Cloud Environment…”, I will continue with this thread by introducing the topic of Software Defined Networks (SDN). The industry has been...
View ArticleClik here to view.
Intel® Xeon Phi™ coprocessor Power Management Part 1: P-States, Reducing...
Right up front, I am going to tell you that P-states are irrelevant, meaning they will not impact the performance of your HPC application. Nevertheless, they are important to your application in a...
View ArticleClik here to view.
Using HLE and RTM with older compilers with tsx-tools
To use HLE/RTM to improve lock scalability the lock library needs to be enabled. If you already have an enabled lock library, like glibc on Linux, you can just use normal locking with that library. If...
View ArticleClik here to view.
Measuring Memory Bandwidth on the Intel® Xeon Phi™ Coprocessor
The memory bandwidth of an application is an important metric to have at your fingertips when optimizing your application. One can measure the memory bandwidth of an application running on the Intel...
View ArticleThe Scalable Heterogeneous Computing Benchmark Suite (SHOC) for Intel® Xeon Phi™
The Scalable Heterogeneous Computing Benchmark Suite (SHOC https://github.com/vetter/shoc-mic#readme) may be used for measuring performance and stability of Coprocessor based systems. The benchmark...
View ArticleThe Intel Xeon Phi coprocessor: What is it and why should I care? PART 3:...
Part 1 showed how to fit 60+ cores onto a single chip. ...
View ArticleCheck out the Intel® Advisor XE 2013 Update 3..
Intel® Advisor XE 2013 Update 3 guides developers to add parallelism to their existing C/C++ programs. Using this tool, you can identify where most of the time is spent in your code, which of those...
View ArticleRegister for Intel® Software Tools Spring Technical Webinar Presentation...
I will be presenting on May 14th at 11am PDT on the following topic: Design and prototype scalable threading using Intel® Advisor XE Please register for this presentation using the following link:...
View ArticleModern locking
Modern locking Most multi-threaded software uses locking. Lock optimization traditionally has aimed to reduce lock contention, that is make the critical regions smaller. In optimized software, this...
View ArticleIntel(r) Transactional Synchronization Extensions (Intel(r) TSX) profiling...
Intel TSX exposes a speculative execution mode to the programmer to improve locking performance.. Tuning speculation requires heavily on a PMU profiler. This document describes TSX profiling using the...
View ArticleSpeeding Up Your Cloud Environment On Intel® Architecture
In my previous blog, I discussed “Ways to Speeding up Your Cloud Environment…”, I will continue with this thread by introducing the topic of Software Defined Networks (SDN ...
View ArticleIntel® Xeon Phi™ coprocessor Power Management Part 1: P-States, Reducing...
Right up front, I am going to tell you that P-states are irrelevant, meaning they will not impact the performance of your HPC application. Nevertheless, they are important to your application in a...
View ArticleUsing HLE and RTM with older compilers with tsx-tools
To use HLE/RTM to improve lock scalability the lock library needs to be enabled. If you already have an enabled lock library, like glibc ...
View ArticleMeasuring Memory Bandwidth on the Intel® Xeon Phi™ Coprocessor
The memory bandwidth of an application is an important metric to have at your fingertips when optimizing your application. One can measure the memory bandwidth of an application running on the Intel...
View ArticleWeb Resources about Intel® Transactional Synchronization Extensions
In this blog I list useful technical resources related to Intel® Transactional Synchronization Extensions (Intel TSX). I will try to keep the list up-to-date as new material becomes available....
View ArticleMonitoring Intel® Transactional Synchronization Extensions with Intel® PCM
After applying a new technology (a new processor, a hardware accelerator, a new instruction, etc) besides measuring the immediate performance delta one requires a method to verify that this technology...
View Article